1. Field of the Invention
The present invention generally relates to the field of microstructure, such as integrated circuits, and, more particularly, to the formation of small elements on a substrate, wherein the dimensions of the elements are significantly less than the resolution of the involved lithographic technique.
2. Description of the Related Art
The trend in recent years to steadily decrease the feature sizes of elements in microstructures, such as circuit elements in integrated circuits, will continue in the near future, wherein reproducible and robust processes have to be established that allow the formation of a huge number of integrated circuits in a cost-efficient manner. Presently, sophisticated integrated circuits that are available as mass products include elements having dimensions which are well below the optical resolution of the lithography apparatus used for transferring a pattern from a mask to the substrate. Minimum dimensions of circuit elements are presently 100 nm and less, wherein the wavelength of radiation used for optically transferring patterns from the mask to the substrate surface are in the deep ultraviolet range, down to approximately 193 nm. In this wavelength range, the absorption of optical transmissive elements, such as lenses, is considerable and will drastically increase with a further reduction of the wavelength. Thus, merely reducing the wavelength of light sources for lithography apparatus is not a straightforward development and may not easily be implemented in mass production of circuit elements having feature sizes of 50 nm and less.
The total resolution of reliably transferring circuit patterns from a mask to a substrate is determined, on the one hand, by the intrinsic optical resolution of the photolithography apparatus, the characteristics of materials involved in the photolithography patterning process, such as the photoresist and any anti-reflective coatings (ARC) that are provided to minimize deleterious scattering and standing wave effects in the photoresist, and by deposition and etch procedures involved in forming the resist and ARC layers and etching these layers after exposure. In particular, the highly non-linear behavior of the photoresist, in combination with sophisticated ARC layers and lithography mask techniques, allows the formation of resist patterns having dimensions considerably below the intrinsic optical resolution of the photolithography apparatus. Additionally, further post-lithography trim etch processes may be applied to further reduce the feature sizes of the resist pattern that will serve as an etch mask in subsequent anisotropic steps for transferring the resist pattern into the underlying material layer.
With reference to FIGS. 1a-1c, a typical conventional process flow for forming a gate electrode of a field effect transistor will now be described. The gate electrode has a design dimension in the lateral direction, that is also referred to as gate length, on the order of 100 nm or less, and the gate electrode extends in the longitudinal direction, i.e., a direction perpendicular to the plane of the drawings, for a distance of a few hundred nanometers. The gate length of a field effect transistor is a critical dimension in that it significantly determines the electrical characteristics of the device and also provides for the capability of reducing the total area occupied by the field effect transistor. However, with the scaling of the gate length, not only the size of the field effect transistors is decreased, but also the dimensions of corresponding contact areas, conductive lines, vias and the like are subjected to a miniaturization, so that a sophisticated imagery is also necessary for these circuit elements.
In FIG. 1a, a semiconductor structure 100 comprises a substrate 101, which may, for example, be a semiconductor substrate, such as a silicon substrate, or any other appropriate substrate having formed thereon a semiconductor-containing layer that allows the formation of the required circuit elements. In particular, the substrate 101 may be a so-called SOI (silicon-on-insulator) substrate. A gate insulation layer 102 is formed on the substrate 101, the thickness of which is adapted to the design gate length. A layer of gate electrode material 103 is formed on the gate insulation layer 102 and may be comprised of any material that is appropriate for forming a gate electrode. If, for instance, a typical silicon-based semiconductor structure is considered, the gate electrode material 103 may preferably be polycrystalline silicon, which is also referred to as polysilicon. For sophisticated silicon-based integrated circuits, a thickness of the layer 103 is in the range of several hundred nanometers. On top of the layer 103 of gate electrode material, an ARC layer 104 is formed, the optical characteristics and the thickness of which are adjusted to the characteristics of the underlying layer 103 and of a photoresist layer 105 formed on top of the ARC layer 104. As previously noted, the ARC layer 104 is designed to minimize scattering and back-reflection of light from the underlying layer 103. Silicon oxynitride is frequently used as the ARC layer since the optical characteristics, such as the complex index of refraction, may be easily adjusted by varying the amount of oxygen, nitrogen and silicon during the deposition of the ARC layer 104. Moreover, the optical characteristics of the photoresist layer 105 and the ARC layer 104 are designed to minimize the formation of standing wave patterns in the photoresist layer 105.
The semiconductor structure 100 is formed according to well-established process steps and the description of these steps is omitted. Subsequently, the semiconductor structure 100 is exposed to deep UV radiation 106 to transfer a required feature pattern from a mask (not shown) into the photoresist layer 105. By means of sophisticated mask and photolithography techniques, including the precisely adjusted ARC layer 104 and the photoresist layer 105, features may be imaged into the photoresist layer 105 having dimensions beyond the wavelength of the deep UV radiation 106.
FIG. 1b schematically shows the semiconductor structure 100 after developing the photoresist layer 105, including associated post-exposure techniques, such as baking and the like, to create a resist feature 105A. A lateral dimension 107 of the feature 105A may be well beyond the wavelength of the deep UV radiation 106, and is limited by the plurality of highly complex lithography processes. Subsequently, the semiconductor structure 100 is subjected to an anisotropic etch process, indicated by 108, wherein the resist feature 105A acts as an etch mask.
FIG. 1c shows the semiconductor structure 100 after completion of the etch process in which a gate electrode, also referred to as 103, is obtained, covered by the residual ARC layer 104 and the resist feature 105A. The lateral extension 109 of the gate electrode 103, i.e., the gate length, is substantially determined by the lateral extension 107 of the resist feature 105A. After the removal of the resist feature 105A and the ARC layer 104, the gate electrode 103 may be subjected to further etch processes in order to further reduce the gate length 109. For example, an etch process may be employed in which the etch rate is substantially isotropic or at least exhibits a relatively high lateral component. By using such etch processes, however, the height of the gate electrode 103 and, more importantly, the gate insulation layer 102 are also affected, thereby possibly compromising the quality of the gate insulation layer 102.
As a result, the conventional processing allows the formation of feature sizes well beyond the wavelength of the radiation used for optically transferring images from a mask to a substrate. However, a conventional process flow relies on a plurality of complex processes to reduce the feature size of the resist feature 105A and to further reduce the dimensions of a circuit element obtained by etching a material layer using the resist pattern as an etch mask. The controllability of the final etch process and the integrity of an underlying layer are difficult to maintain. Moreover, any change in one of the process recipes, for instance the employment of a different exposure wavelength, requires corresponding changes in preceding and following processes, so that a further scaling of feature sizes typically requires a great deal of effort and time to obtain a robust-process sequence that is appropriate for mass production.
In view of the above explained problems, a need exists for a method that allows the scaling of feature sizes well beyond the resolution of the involved photolithography process, wherein well-established and controllable processes ensure high reliability and a shorter development time of a corresponding process sequence.